A non-volatile semiconductor memory device provided with memory cells has been known. The memory cell is comprised of a large-area capacity transistor using a well as a control gate, a writing/erasing transistor used for writing and erasing data, and a reading transistor for reading out data. In the memory cell, the capacity transistor, the writing/erasing transistor, and the reading transistor share a floating gate (see, e.g. Patent Literature 1).
Patent Literature 1 (Japanese Patent Laid-Open No. 2011-23567) discloses a non-volatile semiconductor memory device having a triple well structure in which an N-type embedded well DMW (deep well) is disposed on a semiconductor substrate IS composed of a P-type single crystal silicon. P-type wells HPW1, HPW2, and HPW3 are disposed in the embedded well DNW. Patent Literature 1 will now be described. Here, reference signs assigned to constituent elements in the Patent Literature 1 are used in the following description.
As illustrated in FIGS. 5 and 9 in the Patent Literature 1, a capacity section CWE for writing and erasing data is formed as a writing/erasing transistor in the P-type well HPW2. A capacity section C is formed as a capacity transistor in the P-type well HPW1. An MIS/FFT (Metal Insulator Semiconductor Field Effect Transistor) QR for reading data is formed as a reading transistor in the P-type well HPW3.
In the non-volatile semiconductor memory device having the above-described configuration described in the Patent Literature 1, 9 [V] is applied to the well HPW1, in which the capacity section C is formed, while −9 [V] is applied to the well HPW2, in which the capacity section CWE is formed (see FIG. 9 in the Patent Literature 1), during a data writing operation. Due to a tunneling effect in the capacity section CWE, electrons are injected into a floating gate, so that data is written. Here, in the non-volatile semiconductor memory device, when the voltage at the well HPW1 is 9 [V], the well HPW1 and the embedded well DNW are in a forward direction of a PN junction, so that a voltage at the embedded well DNW reaches 9 [V] or less even if a voltage is not applied externally to the embedded well DNW.
Therefore, in the Patent Literature 1, 9 [V] is applied to the embedded well DNW from a conductor section 7b in a semiconductor region 8a so that a bipolar operation to the semiconductor substrate IS can be prevented (see FIG. 9 in the Patent Literature 1). Thus, in the Patent Literature 1, a reverse bias of 18 [V] is applied to a junction portion between the embedded well DNW and the P-type well HPW2, in which the capacity section CWE for writing and erasing data is formed. For this reason, it is necessary to reduce the concentrations of impurities in the well HPW2 and in the embedded well DNW so that the well HPW2 and the embedded well DNW withstand high voltages.